1. Field of the Invention
The present invention relates to a structure of metal-oxide-semiconductor flip-flop, particularly to a flip-flop implemented with metal-oxide semiconductors using a single low-voltage power supply and a control method thereof.
2. Description of the Related Art
With the emerging demand for a low power consumption semiconductor, the supply voltage of an integrated chip keeps falling. Based on the multi-threshold CMOS technology (MTCMOS), the supply voltages of several designs have been reduced to as small as 0.5 V. They can be implemented by a bulk MTCMOS technology or a very complex SOI (silicon-on-insulator) technology, and many kinds of MOSFET's with different threshold voltages are needed. Refer to FIG. 1 a schematic diagram of the circuit structure of a conventional super cut-off CMOS (SCCMOS). The flip-flop is composed of components 14, 16, 18, and the flip-flop and a combinational circuit 12 are connected to a virtual power supply VDDV. This circuit structure has been shown to achieve a picoampere sleep-mode leakage current per logic gate with using only low-MOSFET's for a 0.5-V functional core. It can be applied with the SOI or bulk CMOS technology. However, in comparison with the conventional flip-flop, in the SCCMOS, a backup SRAM cell 18 is needed to accompany the flip-flop 14, 16 for retaining data in sleep mode. In addition to a 0.5V supply voltage, an extra −0.5V VSS must be applied to the SRAM cell 18 to enhance the driving capability during wake-up.
With respect to the operation of the SCCMOS, refer to FIG. 2. In the active mode, the external sleep control signal SLP is 1, and the internal clock signal CK is anti-phase to the external clock signal CKE in order to match with the negative-edge-triggered SAFF (sense-amplifier-based flip-flop); the control signal VG is 0, and the power switch 10 is switched on, and then the combinational circuit 12 can obtain current to work normally; the sleep control signal for the flip-flop WL is at a high-level voltage, and the SRAM cell 18 is closed, and the SCCMOS flip-flop works normally. In the sleep mode, the external sleep control signal SLP becomes 0, and the internal clock signal CK stops, and the control signal VG equals VDD+0.4V, and the leakage currents of the combinational circuit 12 and the master stage 14 and the slave stage 16 of the flip-flop are controlled by the power switch 10. Next, WL becomes −0.5V for a short period of time, and the CMOS's 182, 184 open to store the values originally in the flip-flop into N1 or N2 of the SRAM cell 18. When out of the sleep mode, SLP backs to the high level, and the control signal VG backs to 0 to charge the virtual power supply VDDV, and WL backs to −0.5V again for a short period of time, and the values in the SRAM cell 18 is written back to the nodes Q/QB of the flip-flop; lastly, after all the signals are resumed, the internal clock CK works again, and the flip-flop enters into the active mode. From the operational procedures described above, it is found that the problems primarily come from the SRAM cell 18 and the sleep control signal WL of the flip-flop. In addition to an extra −0.5V supply voltage, the WL voltage swing between −0.5V and VDD, and its timing is hard to control. Further, the flip-flop 14, 16, 18 and the combinational circuit 12 share the common virtual power supply VDDV controlled by a voltage switch, which will obviously lower the speed and the stability of the flip-flop.
Owing to the problems discussed above, the present invention proposes a flip-flop implemented with metal-oxide semiconductors using a single low-voltage power supply (single-low-voltage MOS, SLVMOS) and a control method thereof in order to overcome the problems.